Section 4: CPU Instruction Execution

The Big Picture: An Assembly Line for One Instruction

Every instruction the CPU runs goes through the same steps, like a car going through a factory: get the parts, read the plan, build, store. This section walks through those steps one by one.

4.1 The Instruction Lifecycle

Every instruction (from Windows, a game or a background service) goes through the same basic lifecycle. Classic CPU design splits it into five stages:

┌────────┐   ┌─────────┐   ┌─────────┐   ┌─────────┐   ┌───────────┐
│ FETCH  │──►│ DECODE  │──►│ EXECUTE │──►│ MEMORY  │──►│ WRITEBACK │
└────────┘   └─────────┘   └─────────┘   └─────────┘   └───────────┘
 get the      figure out    perform the   read/write    store the
 instruction  what it       operation     memory if     result
 from memory  means         (ALU work)    needed        (register)

This five-stage split (Fetch, Decode, Execute, Memory, Writeback) comes from the classic RISC pipeline model. (RISC means a design with a small set of simple instructions.) It is the clearest way to see what "running an instruction" involves. Real modern CPUs have many more internal stages (often 14–20+), but they all map back to this same idea.

4.2 Fetch Stage

What happens: The CPU gets the next instruction from memory. It uses a special register called the Program Counter (PC), also called the Instruction Pointer. The PC always holds the address of the next instruction. Think of it as a finger on the page showing where you are reading.

1. Read the address held in the Program Counter
2. Get the instruction stored at that address (ideally from the L1 instruction cache, see Section 3)
3. Add to the Program Counter so it points to the next instruction

PC = 0x4010  →  Fetch instruction at address 0x4010  →  PC becomes 0x4014

If the instruction is a jump or branch, the Program Counter gets the new target address instead of just moving on. This is how loops and function calls change where the CPU goes next.

4.3 Decode Stage

What happens: The raw bits fetched from memory mean nothing by themselves. The decode stage works out what they mean.

A decoder splits the instruction into two parts:

Raw bits:  00000001 00100000 00011000 01000000
Decoded:   ADD  EAX, EBX      (add the value in EBX to EAX)

This is also where the CPU decides which internal execution unit should handle the instruction. Integer math, decimal (floating-point) math, memory access and branching may each go to a different specialised unit.

4.4 Execute Stage

What happens: The real work is done. Math and logic instructions run in the ALU (Arithmetic Logic Unit), the part of the core that adds, subtracts and compares. Decimal maths uses a dedicated floating-point unit.

What "execute" means for different instructions:

4.5 Memory Stage

What happens: If the instruction needs to read from or write to memory (not just registers), it happens here.

• LOAD instructions: read a value from a memory address into a register
• STORE instructions: write a register's value out to a memory address

Not every instruction needs this stage. An instruction that only uses registers (like ADD EAX, EBX) skips it. This is also where the cache ladder from Section 3 is used: a memory access checks L1, then L2, then L3, then RAM.

4.6 Writeback Stage

What happens: The final result is written back to its destination, almost always a register.

ADD EAX, EBX
   Fetch:     get "ADD EAX, EBX" from memory
   Decode:    opcode = ADD, operands = EAX, EBX
   Execute:   ALU computes EAX + EBX
   Memory:    (skipped — no memory access needed)
   Writeback: result stored back into EAX

When writeback finishes, the instruction is done. The Program Counter (already moved on in the Fetch stage) points to the next instruction, and the whole cycle starts again.

Why this matters: Every speed feature in Section 5 (pipelining, out-of-order execution, speculative execution) is really a clever way to run many copies of this same five-stage cycle at once instead of one at a time.

Summary