Chapter 4 · Motherboard and Hardware Communication

Knowledge Check

7 min read

Try to answer before you open the answers. Guessing is fine; checking your guess is how you learn.

QUICK REVIEW (5 minutes)

  1. What is the job of the PCH (chipset), and what did the CPU take over from the old northbridge?
  2. What does a VRM do?
  3. How many lanes does an x4 PCIe slot have, and what does one lane contain?
  4. What is the main difference between polling and an interrupt?
  5. What does DMA let a device do?
  6. Which sleep state saves your work to disk: S3, S4 or S5?
  7. What is MMIO?
  8. How does a CPU get a 4.5 GHz speed from a 100 MHz base clock?
  9. Which battery keeps the CMOS settings alive?
  10. Why should you never switch off power during a BIOS flash?

ANSWER KEY — DO NOT READ UNTIL YOU'VE ANSWERED

Click to reveal answers

1. The PCH

It connects the slower parts (USB, SATA, network, the BIOS chip) to the CPU. The CPU took over the memory controller and the main graphics PCIe lanes.

2. VRM

It turns the 12 V from the power supply into the ~1 V (at very high current) that the CPU needs, using fast switching.

3. PCIe lanes

4 lanes. One lane has two pairs of wires: one pair sends, one pair receives, both at once.

4. Polling vs interrupt

Polling means the CPU keeps asking "anything yet?". An interrupt means the device tells the CPU when it needs attention, so the CPU can work meanwhile.

5. DMA

Move data directly to or from RAM without the CPU copying every byte.

6. Sleep state

S4 (hibernate), it writes RAM to hiberfil.sys. S3 keeps work in powered RAM; S5 saves nothing.

7. MMIO

Memory-Mapped I/O: a device's control registers appear at memory addresses, so the CPU controls it with normal reads and writes (uncached).

8. 4.5 GHz

100 MHz base clock × 45 multiplier = 4,500 MHz.

9. CMOS battery

The CR2032 coin battery.

10. Flash power loss

A half-written firmware cannot start the PC, which then may be "bricked".

UNDERSTANDING QUESTIONS

Q1. Why did engineers replace the front-side bus with point-to-point links?

Answer The FSB was one shared road: the CPU, RAM and graphics all had to wait their turn, and wide parallel buses are hard to speed up. Point-to-point links (HyperTransport, QPI, Infinity Fabric) are private lines between two things, so there's no waiting and they can run faster.

Q2. Why do fast NICs and NVMe SSDs use MSI-X?

Answer MSI-X gives a device up to 2,048 separate interrupts. The device can give each CPU core its own, so the work is spread evenly and nothing has to share one wire or wait.

Q3. Why is DMA a security risk, and what stops it?

Answer A DMA device can read or write any RAM it wants, even without the CPU knowing, so a bad plug-in device could steal data. An IOMMU (Intel VT-d / AMD-Vi, shown as Kernel DMA Protection in Windows) limits each device to only the memory it was given.

Q4. Why is most PC power delivered at +12 V?

Answer Power = volts × amps. At a higher voltage, the same power needs less current. Less current means thinner wires, less heat and less loss. The VRM then steps it down near the chip.

Q5. Why do cached reads cause trouble with device registers, and how is it avoided?

Answer A cache may return an old copy instead of asking the device. MMIO regions are therefore marked uncacheable so every read really goes to the device.

SCENARIO QUESTIONS (Troubleshooting)

S1. The PC's clock shows the wrong date every time it's switched on, and Windows says "CMOS checksum error". What is the likely cause and fix?

Answer The CR2032 CMOS battery is dead. Replace it (about 3–10 years of life), then re-enter the BIOS settings and the date.

S2. You copy a file between two fast USB drives plugged into the same hub, and speed is low. What would you try?

Answer Everything behind one hub shares its bandwidth. Plug each drive into its own port on the motherboard (ideally a separate controller), and use USB 3 ports and cables.

S3. Your PC freezes with 3% CPU use, and audio crackles. "System interrupts" is very high. What does this suggest?

Answer An interrupt storm or a slow driver/DPC: some device is firing interrupts non-stop. Use a tool like LatencyMon to find the driver, then update or remove it, or unplug the suspect device.

S4. A new graphics card works but only at "x4" in CPU-Z. Why might this be?

Answer The card is in a slot that only has 4 electrical lanes (a long x16-shaped slot can have fewer lanes), or lanes are shared with other slots (bifurcation). Move it to the main x16 slot and read the board manual.

S5. Pressing power makes the fans spin for a second and then everything stops, repeatedly. Which part of Section 1.4 could be involved?

Answer The power-on sequence: the PSU must send "Power Good", and the board must hold the CPU in reset until then. A failing PSU, a short, or a bad component can break that sequence. Test with another PSU, and remove extra cards to look for a short.

INTERVIEW QUESTIONS

I1. Explain the difference between port I/O and memory-mapped I/O.

Answer Port I/O uses a separate x86-only space of 65,536 ports with IN/OUT instructions. MMIO maps device registers into the normal address space, accessed by ordinary loads and stores. Modern devices prefer MMIO.

I2. Describe what happens from a key press to the OS knowing about it.

Answer The keyboard controller raises an interrupt, routed by the (I/O) APIC to a core's local APIC; the CPU looks up the vector in the IDT, runs the ISR in the keyboard driver, which quickly saves the key and defers the rest to a DPC; the CPU then returns to what it was doing.

I3. What does ACPI do?

Answer It lets the OS manage power. Firmware provides tables (written in AML) that describe the hardware and how to change its power state; the OS makes the decisions (sleep, wake, device power).

I4. Why are DMA descriptors usually in rings?

Answer A ring lets the CPU add work at one end while the device takes work from the other, with no waiting or per-job setup. It keeps many jobs in flight, which suits NICs and NVMe.

I5. What causes clock skew and jitter, and why do they limit speed?

Answer Skew comes from different wire lengths and delays; jitter from noise in the clock source. Both move the tick time, eating into the setup and hold margins, so a chip can read wrong data. This sets the maximum safe clock speed.

PRACTICAL TASK

Draw a one-page "map of my PC". Using your results from the Practical Lab, draw (on paper or in a drawing tool) boxes for the CPU, RAM, GPU, SSD, PCH and USB. Connect them with lines and label each line with the bus type and speed (for example, "PCIe 4.0 x16" or "DMI 3.0 x4").

Why This Matters

When something is slow, you can look at the map and see where the shared road is. It also trains you to see the PC as a network of links rather than a pile of parts.

CHAPTER SUMMARY

  • The motherboard connects, powers and times every part. The CPU now has the memory controller and main PCIe lanes; the PCH serves everything else over DMI.
  • Buses are the roads: PCIe (lanes, generations), USB (tree of hubs), SATA/SAS and NVMe, and slow I²C/SMBus.
  • Interrupts let devices get attention without polling: IRQ → PIC/APIC → MSI/MSI-X → IDT → ISR + DPC.
  • DMA lets devices move data without the CPU, using descriptors and rings; cache coherency and the IOMMU keep it correct and safe.
  • Power: PSU rails, VRMs, ACPI, and states S0/S3/S4/S5 plus C- and P-states.
  • I/O: PIO, MMIO with BARs, x86 ports, and enumeration at boot.
  • Clocks: crystals, BCLK × multiplier, clock domains, skew and jitter.
  • Firmware: BIOS/UEFI in SPI flash, CMOS battery, and careful flashing.