Section 3: Interrupts (Hardware)

The Big Picture: Tap on the Shoulder

Imagine you are cooking, and you want to know when the doorbell rings. You have two choices:

1. Polling — walk to the door every 10 seconds and look. Wasteful: you leave the stove again and again.
2. Interrupt — keep cooking. When someone rings the bell, you stop and answer. Efficient.

Computers face the same choice. The keyboard, mouse, network card and disk all need the CPU's attention at unpredictable times. If the CPU kept checking each one ("anything yet? anything yet?"), it would waste almost all its time. Instead, a device sends an interrupt: a short electrical signal that means "CPU, stop what you're doing and look at me."

POLLING (wasteful)                  INTERRUPT (efficient)

CPU: any key? no.                   CPU: ... working on your spreadsheet ...
CPU: any key? no.                   KEY PRESSED ──► interrupt!
CPU: any key? no.                   CPU: saves its place, handles the key,
CPU: any key? YES.                        goes back to the spreadsheet.

3.1 Hardware Interrupts and IRQ Numbers

What it is: A hardware interrupt is a signal from a device. Each device line was historically given a number called an IRQ (Interrupt ReQuest). The number tells the CPU who is calling.

The classic PC numbers (you will still see some of these today):

Interrupts are not the same as errors. The word "exception" is used for errors inside the CPU itself (for example dividing by zero). Interrupts come from outside the CPU, from devices.

3.2 Interrupt Controllers: PIC and APIC

What it is: The CPU has only one "interrupt in" pin. Dozens of devices want to use it. So a helper chip sits between them: the interrupt controller. It collects all the signals, decides which is most important, and passes one at a time to the CPU.

The old helper: PIC. The 8259 PIC (Programmable Interrupt Controller) handled 8 lines. PCs used two PICs chained together, giving 15 usable IRQs (one line is used to connect the two).

Devices ─► [ PIC #2 ]──┐
(IRQ 8–15)             │ (uses IRQ 2)
Devices ─► [ PIC #1 ]──┴──► CPU
(IRQ 0–7)

Its problems: too few lines, devices had to share lines (causing conflicts), and it only worked with one CPU.

The modern helper: APIC. The APIC (Advanced PIC) fixes all of that. It has two kinds of pieces:

 Devices ──► I/O APIC ──┬──► Local APIC (core 0)
                        ├──► Local APIC (core 1)
                        ├──► Local APIC (core 2)
                        └──► Local APIC (core 3)

Benefits: 24 or more lines, works with many cores, and the system can spread interrupts across cores so no single core is overloaded.

3.3 MSI (Message Signaled Interrupts)

What it is: The newest way. Instead of using a dedicated wire to raise an interrupt, a PCIe device simply writes a small message into memory at a special address. The chipset sees that write and turns it into an interrupt. No wire needed.

Why it is better:

There are two versions:

A fast network card or NVMe SSD uses many interrupts, one per CPU core, so the work is shared evenly. This is a big reason modern hardware is fast.

On Windows: Open Device Manager → View → Resources by type. Open Interrupt request (IRQ). Normal old IRQs show as small positive numbers like (ISA) 1. Devices that use MSI show negative numbers like -2147483644. If you see a negative number, that device uses MSI. That is normal and good.

3.4 Interrupt Routing

What it is: The path an interrupt takes from the device to the code that handles it.

1. Device raises the interrupt
        │      (a wire to the I/O APIC, OR an MSI memory write)
        ▼
2. I/O APIC / chipset picks a target core
        ▼
3. That core's Local APIC receives it
        ▼
4. The CPU finishes its current instruction, then looks up the
   interrupt's number in the IDT (Interrupt Descriptor Table)
        ▼
5. The IDT gives the address of the right handler code
        ▼
6. Handler runs (the ISR, see 3.5)

The IDT is simply a table in memory: "interrupt #33 → run the code at this address." The operating system fills it in at boot. Remember the virtual memory table from Chapter 3? This is the same idea: a lookup table the CPU consults.

Choosing the core. Windows can bind a device's interrupt to a particular core, or spread them across all cores. The default is usually the best.

3.5 Interrupt Service Routine (ISR)

What it is: The ISR is the small piece of code, inside the device's driver, that runs when its interrupt arrives.

Rule number one: be quick. While an ISR runs, other interrupts of lower importance may be held back. So the ISR does only the urgent part and leaves the long part for later.

Network packet arrives
        │
        ▼
┌─────────────────────────────┐
│ ISR  (microseconds)         │   "Got it. Mark it. Turn the alarm off."
└──────────────┬──────────────┘
               ▼
┌─────────────────────────────┐
│ DPC (Deferred Procedure Call)│   "Now, with a bit more time,
│  a bit later, still quick   │    process the packet properly."
└─────────────────────────────┘

This two-step split is how Windows works: the ISR is fast and urgent, and the DPC does the rest a moment later.

What the CPU does around an ISR:

1. Finishes the current instruction.
2. Saves its place (the current instruction address and a few registers).
3. Jumps to the ISR.
4. After the ISR, restores its place and carries on as if nothing happened.

When interrupts go wrong:

Free tools such as LatencyMon show which driver is the slow one. In Task Manager, a high "System interrupts" entry (in Details) is a warning sign.

Summary